The Compact Model Coalition (CMC) has adopted a model from French lab Leti for fully-depleted silicon-on-insulator (FD-SoI) chip simulation. Called L-UTSOI, it was “proven by the industry and its standardisation will ensure long-term access and maintenance in EDA tools for FD-SOI designers”, according to Leti. Available to Coalition members now, it will be implemented in major versions ...

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