Imec and Cadence have taped out the industry’s first 3nm test chip tapeout. The tapeout project, geared toward advancing 3nm chip design, was completed using EUV and 193 immersion (193i) lithography-oriented design rules and the Cadence Innovus Implementation System and Genus Synthesis Solution. Imec utilized a common industry 64-bit CPU for the test chip with ...

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