Rambus has announced an interface  for HBM2E memory consisting of co-verified PHY and memory controller. Operating at a top speed of 3.2 Gbps over a 1024-bit wide interface, the interface can deliver 410 GB/s of bandwidth with a single HBM2E DRAM stack. In addition to the speed jump from 2.0 to 3.2 Gbps for HBM2E ...

This story continues at Integrated HBM2E interface

Or just read more coverage at Electronics Weekly