SiLabs aims at 56Gbit/s comms with low-jitter clock chips

Silicon Labs is aiming at 56Gbit/s PAM-4 serdes and 112Gbit/s serial applications with a set of clock generators, jitter attenuating clocks and voltage-controlled crystal oscillators. Si5391 is an ‘any-frequency’ clock generator with up to 12 outputs and sub-100fs RMS phase jitter. A precision calibrated version (‘P-grade’) typically achieves 69fs RMS phase jitter and can create the ...

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