Moortec puts PVT IP on 40nm

Moortec, the Plymouth specialist in PVT IP, has developed a PVT IP  for TSMC’s 40nm ULP CMOS technology. By detecting process variability for each chip manufactured and monitoring the dynamic changes to temperature and voltage supply conditions, the IP can be used to enable continuous Dynamic Frequency and Voltage Scaling (DVFS) and Adaptive Voltage Scaling ...

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Panasonic starts production of ultra-low transmission loss PCB material.

Panasonic  has started to mass produce an ultra-low transmission loss circuit board material that is suitable for use in semiconductor packages and modules. With data communications becoming larger in volume and faster, a demand has arisen for new materials used in semiconductor packages and modules. From its original resin design technology, the company has developed ...

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SiLabs aims at 56Gbit/s comms with low-jitter clock chips

Silicon Labs is aiming at 56Gbit/s PAM-4 serdes and 112Gbit/s serial applications with a set of clock generators, jitter attenuating clocks and voltage-controlled crystal oscillators. Si5391 is an ‘any-frequency’ clock generator with up to 12 outputs and sub-100fs RMS phase jitter. A precision calibrated version (‘P-grade’) typically achieves 69fs RMS phase jitter and can create the ...

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TSMC refines N7 technology; N5 in development

DAC 2018: Foundry TSMC confirmed that it has refined the N7 technology it introduced at last year’s DAC, with N7+, using EUV layers to realise a smaller, denser standard cell to reduce power requirements and increase density by up to 20%. The denser standard cell increases reliability, exploiting EUV layers for greater accuracy in the ...

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