A process flow for six-transistor (6T) SRAM suitable for 5nm chips has been created by Belgian research lab Imec working with Unisantis Electronics Singapore. It uses surrounding gate transistors (SGTs) – a vertical gate-all-around architecture developed at Unisantis – to squeeze the cell into foot prints between 0.0184 and 0.0205μm2. “Studies show that the vertical gate-all-around SGT-based ...

This story continues at Gate-all-around key to 5nm SRAM cell

Or just read more coverage at Electronics Weekly