Chip suppliers focus on high resolution audio
High resolution audio is the music industry’s next focus, according to a new industry report, which also said that ‘lossless’ streaming subscriptions are expected to account for almost 25% of all music subscriptions by 2020. But this does not mean the lower quality MP3 music file format is going to be replaced anytime soon. “Amazingly, ...
On Semi has issued a reference design implementing Qualcomm’s Quick Charge 3.0 protocol – which supports High Voltage Dedicated Charging Port (HVDCP) Class A and Class B specifications.
It is based around the firm’s NCP4371 secondary side charge controller, which allows charger USB-bus voltage to be varied in steps from 3.6 to 20V based on requests from the phone or tablet.
Also on the secondary side of the reference design is On’s NCP4305 synchronous rectification controller. On the primary side is the NCP1361 PSR quasi-resonant valley-switching PWM controller.
“The combination of these two controllers enables a high efficiency design meeting CoC Tier-2 [see below] requirements for chargers. The availability of a reference design as well as certified conformance from UL aids development of small form factor chargers,” said On.
The European Commission Code of Conduct (CoC) covers single voltage external ac-dc and ac-ac power supplies with output ratings between 300mW and 250W for, among other things: ac adapters, battery chargers for phones, domestic appliances, power tools and IT equipment. Tier-2 is the more stringent requirement, for example specifying 75mW stand-by for supplies from 300mA to 49W.
NCP4371 comes in an 8pin SOIC.
Ingenic has introduced ‘X Series’, a family of 1GHz MIPS-cored microcontrollers aimed at the more complex end of human-machine interfacing – face, voice and fingerprint recognition, as well as audio and security.
The core has what MIPS describes as a “mobile-level” feature set with a double-precision floating-point unit and multimedia/audio acceleration instructions for lossless audio decoding. There is also a multimedia processing block, and security subsystem for AES and RSA up to 2,048 bits..
Power is 90µW/MHz and 200µW stand-by.
The first member of the family is the X1000, aimed at applications such as connected speakers, intelligent toys, image analytics (car number plate recognition, face and fingerprint detection), or smart household appliances.
Multimedia
The multimedia engine audio codec supports 24bit resolution and up to 95dB signal-to-noise ratio.
There is also an always-on, low-power voice recognition engine with hardware filters to detect and act on voice commands. “For example, developers can use a four-microphone array to perform noise cancellation and voice positioning,” said MIPS, which is promoting the microcontroller.
For cameras, there is an encoder that encodes 1,280×720 pictures in <30ms.
Development
For development there is a board running Linux, branded Phoenix, which has an X1000 with 16Mbyte flash, a micro SD slot (up to 32GB), 802.11b/g/n Wi-Fi, Bluetooth 4.0, 10/100M Ethernet, USB OTG, three microphone ports and JTAG. Expansion headers are provided for a display, camera and ZigBee.
“If developers want to quickly integrate these new chips in their products, Ingenic will also supply another computing module named Halley2 that includes the X1000 SoC, 16Mbyte of flash memory, a dedicated Wi-Fi and Bluetooth chip, and a power management IC,” said MIPS.
| CPU | XBurst CPU 1.0GHz, MIPS-based Hardware FPU, SIMD 16kbyte L1 I-cache 16kbyte L1 D-cache 128kbyte L2 unified cache |
| Memory | Support 16bit LPDDR, DDR2, DDR3 32Mbyte LPDDR in package |
| Display | 8, 9, 16bit parallel interface SLCD |
| Camera | 8bit parallel interface, up to 2.0Mpixel Hardware JPEG encode 1,280×720 30fps Support CCIR656 input |
| Audio | Audio codec with stereo ADC and DAC DMIC controller with voice trigger engine I2S/SPDIF for external audio codec PCM interface, master and slave mode |
| Other interfaces | I2C (x3) SPI USB 2.0HS OTG MMC/SD/SDIO (x2) Full-duplex UART (x3) Serial flash interface Smart card interface I2S PCM Ethernet MAC |
| Security | 1kbit OTP memory Hardware RSA (2048bit) and AES (256bit) Security boot |
| Package | 13 x 13 x 1.2mm, BGA-190, 0.8mm pitch |
| OS | Linux 3.0 and later |
Freescale aims ABS chip at motorbikes
Motorcycles get their own anti-lock braking (ABS) chip with Freescale’s MC33SB0400 analogue chip, which includes solenoid power stages, but needs no heatsink.
“Introduction of the products coincides with the upcoming initial implementation of European Commission legislation making the fitment with ABS for all new motorcycles above 125cc to be mandatory beginning 1 January 2016,” said Freescale. “By incorporating these 7x7mm devices into their designs, manufacturers of ECUs [electronic control units] no longer must rely on larger ABS ICs developed for automobiles.”
SB0400 works on both wheel, while for scooters and lighter motorcycles there is the one-wheel-only SB0401.
Made on Freescale’s Smartmos mixed signal process, the devices integrate: wheel speed sensor interface, valve drivers (four or two), motor pump driver, safety switch, watchdog and safety state machine; plus protection and diagnostics for: over-voltage, under-voltage, over-temperature, shorted load and open load. An internal charge pump allows n-channel external mosfets to be used to control the pump and isolate the solenoids.
Information interfaces include: vehicle speed output, warning lamp driver (14O), ISO K-line interface for connection to a plug-in diagnostic tester and 16bit SPI serial bus.
Solenoid drivers are rated at up to 5A (160mO switch) with PWM up to 5kHz. The pump motor pre-driver works up to 500Hz.
The firm’s functional safety programme (Freescale Safe Assure) is available to help system manufacturers with system compliance with functional safety standards ISO 26262 and IEC 61508. www.freescale.com/SafeAssure.
Both ICs are in volume production.
The MC33SB0400 demo board video is a good introduction and not just fluff. Access to the data sheet requires a log-in, although a cut-down version is freely available.
It’s not often you get the chance to name a supercomputer. But the opportunity arose with a competition at Imperial College to christen their recently expanded supercomputer, part of the College’s High Performance Computing Service.
There were more than one hundred entries from students, alumni and staff, with the winner being “Helen”, in recognition of Helen Kemp Porter who was the first female Professor at Imperial.
Professor James Stirling, Provost of Imperial, and Professor Peter Haynes, Academic Champion for High Performance Computing, judged the entries and the winning name was submitted by Kay Barrett, from the university’s Department of ICT (pictured, alongside Professor Stirling and Professor Haynes).
“I was looking at all the great Imperial researchers on our website and Professor Porter’s name really stood out,” said Barrett.
“She was a female pioneer and as a woman working in the technology sector, I thought it was important to recognise the contribution women have made to science throughout history. I am also really chuffed that I now have bragging rights.”
The university amplifies the biography of Professor Porter:
Professor Porter, who passed away in 1987, was a botanist, biologist and biochemist at Imperial and a Fellow of the Royal Society. She was one of the first British scientists to use chromatography, which is the collective term for a set of laboratory techniques that can be used to separate mixtures. She also pioneered the use of radioactive tracers, which can be used to explore the mechanisms of chemical reactions in experiments.
Being appointed the first female professor in 1959 was an important milestone in Porter’s career and a big leap forward for the male-dominated Imperial at the time. She had already been elected Fellow of the Royal Society three years earlier. She also held the role of Head of the Unit of Plant Physiology, which was based at Imperial and funded by the Agricultural Research Council, until her retirement from College in 1964. Professor Porter then became Second Secretary to the Agricultural Research Council, and in 1972, Adviser to the Secretary.
See also: UK supercomputer gets upgrade
Potassium can work with graphite in a potassium-ion battery, claims Oregon State University, which said the last time this possibility was explored was in 1932.
“For decades, people have assumed that potassium couldn’t work with graphite or other bulk carbon anodes in a battery,” said chemist Xiulei Ji. “That assumption is incorrect. It’s really shocking that no one ever reported on this issue for 83 years.”
That said, potassium is a big atom to get into graphite.
In ‘Carbon electrodes for K-ion batteries‘, a paper in the Journal of the American Chemical Society, Ji describes a potassium-graphite cell where “graphite shows moderate rate capability and relatively fast capacity fading” in which potassium reversibly enters graphite in stages with a K:C atom ratio of 2:72, then 3:72 and finally 9:72.
To get over limited cycle life, the team moved away from graphite and synthesised a soft carbon that exhibits “cycle ability and rate capability much superior to that of graphite”, said the University.
But it is still not as good as lithium-carbon
“It’s safe to say that the energy density of a potassium-ion battery [see graph] may never exceed that of lithium-ion batteries,” said Ji. “But they may provide a long cycling life, a high power density, a lot lower cost, and be ready to take the advantage of the existing manufacturing processes of carbon anode materials.”
The hope is that potassium could replace rare and expensive lithium – according to Ji, potassium is 880 times more abundant in the Earth’s crust than lithium – as a charge carrier in batteries for transportation, industry power backup, micro-grid storage, renewable energy storage. Sodium and magnesium are other proposed lithium replacements.
The Weightless SIG has launched a Weightless-N development environment for low power wide area network connectivity in IoT projects.
The development kits include a desktop base station with the same functionality as a commercial grade base station packaged in a non-ruggedised casing, a base station antenna, an end product module mounted on a development carrier board with external connections, a module antenna and a cset of cabling.
The SDK incorporates an ARM Cortex-M3 MCU with 128KB of flash memory. The kit also includes supporting software tools, Simplicity Studio and a GNU C Compiler (GCC), together with a complete user guide.
“Designers have been keenly anticipating the launch of the Weightless SDK – that wait is now over” says Weightless CEO William Webb, “we’re keen to see LPWAN projects commence rapidly so to celebrate the launch we’re making it easy to engage with Weightless technology by offering a limited number of kits available for free.”
Nwave Technologies is making the development kit available at cost and the Weightless SIG is paying this cost making SDKs free to developers. A refund of the membership fee is also being offered by the Weightless SIG to Associate Members that submit product for certification.
Weightless SIG Members get access to all of the open standard specifications, the test specifications, the test and certification programme and the right to sell product using the technology on a royalty free basis.
A team of Australian engineers has built a quantum logic gate in silicon for the first time, making calculations between two qubits of information possible. A crucial quantum computing hurdle has been overcome, according to the University of New South Wales (UNSW).
“High-fidelity two-qubit gates in the solid state that can be manufactured using standard lithographic techniques have so far been limited to superconducting qubits owing to the difficulties of coupling qubits and dephasing in semiconductor systems. Here we present a two-qubit logic gate, which uses single spins in isotopically enriched silicon and is realised by performing single and two-qubit operations in a quantum dot system using the exchange interaction,” said the UNSW team in a Nature abstract for the paper ‘A two-qubit logic gate in silicon‘.
The gate is a ‘controlled NOT’ (CNOT) gate.
A design for a quantum computer chip that would allow for millions of qubits has been patented, and industry partners are sought to make it.
Menno Veldhorst (left in the photo) was lead author of the paper and Professor Andrew Dzurak (right) lead the project. Other UNSW contributors include Henry Yang and Andrea Morello – who leads the quantum spin control research team. Professor Kohei Itoh from Keio University in Japan provided special silicon wafers.
Quantum computers
In classical computers, data is rendered as binary bits, which are always in one of two states: 0 or 1.
A quantum bit (‘qubit’) can exist in both of these states at once – known as a superposition.
A qubit operation exploits this quantum weirdness by allowing many computations to be performed in parallel. According to UNSW, a two-qubit system performs the operation on four values, a three-qubit system on eight, and so on.
“If quantum computers are to become a reality, the ability to conduct one- and two-qubit calculations are essential,” said Dzurak, who jointly led the 2012 team that demonstrated the first ever silicon qubit, also reported in Nature.
In the gate, data is encoded as spin up or spin down – or the superposition of both.
Silicon electron spins have a usable coherence times’, after which data decays to randomness.
In 1998, according to the University, former UNSW researcher Bruce Kane first proposed the idea of using silicon as a base material for quantum computing. In Nature he outlined a silicon-based computer in which single phosphorus atoms in otherwise pure silicon define the qubits.
In 2012 Dzurak and Morello led a team that demonstrated a spin qubit in silicon, but in an atom rather than a transistor.
Last year Dzurak’s team discovered a way to create a qubit with a device similar to a mosfet.
Photo: Menno Veldhorst (left) and project leader Andrew Dzurak in the UNSW laboratory where the experiments were performed.
Tensilica Audio IP
High resolution audio is the music industry’s next focus, according to a new industry report, which also said that ‘lossless’ streaming subscriptions are expected to account for almost 25% of all music subscriptions by 2020.
But this does not mean the lower quality MP3 music file format is going to be replaced anytime soon.
“Amazingly, the MP3 music format is 25 years old, and it still has an important part to play in today’s music landscape. However, because it compresses the music file for easier storage and internet transfer, the music quality invariably suffers,” said Peter Cooney, Principal Analyst & Director of SAR Insight & Consulting.
As broadband coverage widens and mobile download speeds increase thee will be an opportunity for higher resolution audio.
According to the latest report from SAR Insight & Consulting, called: ‘High Resolution Audio: Creating Opportunities Across the Audio Ecosystem; State of the Industry Today and Future Market Growth’ the music industry as a whole has been slow to embrace HRA, but the link up between the Consumer Electronics Association, The Digital Entertainment Group, Japan Audio Society and major music labels, such as Sony Music Entertainment, Universal Music Group and Warner Music Group in 2014 to define and promote high resolution audio formats through formal definitions for master quality sources, was a major step forward.
“There is a strong incentive for the music industry to drive consumer awareness and, therefore, increase interest in HRA music as this can be used to reinvigorate the download market, help increase prices for a premium product, and help to drive premium streaming services,” said Cooney.
HRA also has the support of major artists, such as the Foo Fighters who, earlier this year, teamed up with Sony Music to promote the lossless format. But there are still barriers to market.
“Consumers, particularly younger people, have become increasingly accustomed to or have grown up only listening to compressed audio. This is perhaps the most difficult hurdle to overcome for the music industry as a whole if it is to drive HRA to the mass market,” said Cooney.
Motorcycles get their own anti-lock braking (ABS) chip with Freescale’s MC33SB0400 analogue chip, which includes solenoid power stages, but needs no heatsink.
“Introduction of the products coincides with the upcoming initial implementation of European Commission legislation making the fitment with ABS for all new motorcycles above 125cc to be mandatory beginning 1 January 2016,” said Freescale. “By incorporating these 7x7mm devices into their designs, manufacturers of ECUs [electronic control units] no longer must rely on larger ABS ICs developed for automobiles.”
SB0400 works on both wheel, while for scooters and lighter motorcycles there is the one-wheel-only SB0401.
Made on Freescale’s Smartmos mixed signal process, the devices integrate: wheel speed sensor interface, valve drivers (four or two), motor pump driver, safety switch, watchdog and safety state machine; plus protection and diagnostics for: over-voltage, under-voltage, over-temperature, shorted load and open load. An internal charge pump allows n-channel external mosfets to be used to control the pump and isolate the solenoids.
Information interfaces include: vehicle speed output, warning lamp driver (14Ω), ISO K-line interface for connection to a plug-in diagnostic tester and 16bit SPI serial bus.
Solenoid drivers are rated at up to 5A (160mΩ switch) with PWM up to 5kHz. The pump motor pre-driver works up to 500Hz.
The firm’s functional safety programme (Freescale Safe Assure) is available to help system manufacturers with system compliance with functional safety standards ISO 26262 and IEC 61508. www.freescale.com/SafeAssure.
Both ICs are in volume production.
The MC33SB0400 demo board video is a good introduction and not just fluff. Access to the data sheet requires a log-in, although a cut-down version is freely available.
Freescale aims ABS chip at motorbikes – SB0400 SB0401
