Finding intermittent errors is always difficult and in complex SoC design it is becoming a significant problem.

The problem arises when designs use shared resources on the chip such as bus bandwidth and memory.

For example, a processor can be waiting for a response from another sub-system via an on-chip bus such as AXI or OCP, but the response never arrives This is becoming such as design issue that it has a name – bus deadlock.

This problem is what UK-based silicon IP firm UltraSoC has addressed by adding deadlock detection to its SoC analysis, profiling and debug.

“Our customers tell us that intermittent deadlock and stall conditions are amongst the hardest problems to solve in their SoC designs. These conditions are a major contributor to the current crisis in the SoC industry,” said Gadge Panesar, UltraSoC, chief technology officer.

According to Panesar, UltraSoC’s approach is  to allow designers to effectively “look inside” the SoC design at wire speed, during normal operation.

The claim is that this can address the most likely issues which cause devices to fail intermittently and unpredictably, including bus and software deadlocks.

The company has created an on-chip bus monitor that is protocol-aware and can be triggered when the time taken for a bus transaction exceeds a programmable limit. When triggered by a deadlocked transaction, the system identifies the complete transaction ID and address, guiding the engineer’s attention to both the master and slave of the problem.

Another problem is when two different software processes use a locking mechanism to govern shared access to a processor core or hardware peripheral. Each believes the other has locked its access to the shared resources.

An on-chip status monitor which can be used to detect the fault condition, halt the processors and initiate data capture to isolate the problem. As multi-core systems and heterogenous architectures become more common this becomes ever more important.

UltraSoc said its IP will support different bus protocols and processor families (including ARM, MIPS, Xtensa, CEVA and others).

UltraSoC will be demonstrating its new deadlock detection capabilities at ARM TechCon in Santa Clara 10 – 12 November.

Richard Wilson

On-chip error detection makes SoCs more reliable, says UltraSoC

Finding an intermittent error is always difficult and in complex SoC design it is becoming a significant problem.

The problem arises when designs use shared resources on the chip such as bus bandwidth and memory.

For example, a processor can be waiting for a response from another sub-system via an on-chip bus such as AXI or OCP, but the response never arrives This is becoming such as design issue that it has a name – bus deadlock.

This problem is what UK-based silicon IP firm UltraSoC has addressed by adding deadlock detection to its SoC analysis, profiling and debug.

“Our customers tell us that intermittent deadlock and stall conditions are amongst the hardest problems to solve in their SoC designs. These conditions are a major contributor to the current crisis in the SoC industry,” said Gadge Panesar, UltraSoC, chief technology officer.

According to Panesar, UltraSoC’s approach is  to allow designers to effectively “look inside” the SoC design at wire speed, during normal operation.

The claim is that this can address the most likely issues which cause devices to fail intermittently and unpredictably, including bus and software deadlocks.

The company has created an on-chip bus monitor that is protocol-aware and can be triggered when the time taken for a bus transaction exceeds a programmable limit. When triggered by a deadlocked transaction, the system identifies the complete transaction ID and address, guiding the engineer’s attention to both the master and slave of the problem.

Another problem is when two different software processes use a locking mechanism to govern shared access to a processor core or hardware peripheral. Each believes the other has locked its access to the shared resources.

An on-chip status monitor which can be used to detect the fault condition, halt the processors and initiate data capture to isolate the problem. As multi-core systems and heterogenous architectures become more common this becomes ever more important.

UltraSoc said its IP will support different bus protocols and processor families (including ARM, MIPS, Xtensa, CEVA and others).

UltraSoC will be demonstrating its new deadlock detection capabilities at ARM TechCon in Santa Clara 10 – 12 November.

Richard Wilson

Finding intermittent errors is always difficult and in complex SoC design it is becoming a significant problem.

The problem arises when designs use shared resources on the chip such as bus bandwidth and memory.

For example, a processor can be waiting for a response from another sub-system via an on-chip bus such as AXI or OCP, but the response never arrives This is becoming such as design issue that it has a name – bus deadlock.

This problem is what UK-based silicon IP firm UltraSoC has addressed by adding deadlock detection to its SoC analysis, profiling and debug.

“Our customers tell us that intermittent deadlock and stall conditions are amongst the hardest problems to solve in their SoC designs. These conditions are a major contributor to the current crisis in the SoC industry,” said Gadge Panesar, UltraSoC, chief technology officer.

According to Panesar, UltraSoC’s approach is  to allow designers to effectively “look inside” the SoC design at wire speed, during normal operation.

The claim is that this can address the most likely issues which cause devices to fail intermittently and unpredictably, including bus and software deadlocks.

The company has created an on-chip bus monitor that is protocol-aware and can be triggered when the time taken for a bus transaction exceeds a programmable limit. When triggered by a deadlocked transaction, the system identifies the complete transaction ID and address, guiding the engineer’s attention to both the master and slave of the problem.

Another problem is when two different software processes use a locking mechanism to govern shared access to a processor core or hardware peripheral. Each believes the other has locked its access to the shared resources.

An on-chip status monitor which can be used to detect the fault condition, halt the processors and initiate data capture to isolate the problem. As multi-core systems and heterogenous architectures become more common this becomes ever more important.

UltraSoc said its IP will support different bus protocols and processor families (including ARM, MIPS, Xtensa, CEVA and others).

UltraSoC will be demonstrating its new deadlock detection capabilities at ARM TechCon in Santa Clara 10 – 12 November.

Richard Wilson