Author Archives: richard wilson

Car makers going big on 3D touch control, says UK sensor firm

Car manufacturers are adopting touch control technology in a big way. So much so that UK-based touch sensor firm Peratech has expanded resources in its North Yorkshire-based headquarters.

Car makers going big on 3D touch control, says Peratech

Car makers going big on 3D touch control, says Peratech

The company said it is seeing its QTC force touch sensors being integrated under in-car surfaces such as plastics, rubbers, wood, leather, metals and glass.

Neil Jarvie, Peratech sales v-p, says that the capability to incorporate pressure sensing that capacitive touch sensing does not provide is important for Tier 1 automotive companies.

The matrix sensors are designed to track multiple touches for position on X and Y axes and independent pressure sensing along the Z-axis.

According to Jarvie, this allows designers to reduce button count in the centre stack, steering wheel and other cockpit surfaces.

“Replace the top surface of buttons with a display, and you have a Human Machine Interface (HMI) that is reconfigurable on the fly,” added Jarvie.

“Because the sensors aren’t affected by the electromagnetic interference of a display, we can make a display panel showing switches, sliders and knobs that actually work.”

The firm’s sensors are tested for operation through cycles of -40 to +100 degrees C, which is the operational temperature range that the automotive industry requires.

“The requirement for a smart force touch display panel, first and foremost, is that is always works,” said Jarvie.

Richard Wilson

Car makers going big on 3D touch control, says UK sensor firm

Car manufacturers are adopting touch control technology in a big way. So much so that UK-based touch sensor firm Peratech has expanded resources in its North Yorkshire-based headquarters.

Car makers going big on 3D touch control, says Peratech

Car makers going big on 3D touch control, says Peratech

The company said it is seeing its QTC force touch sensors being integrated under in-car surfaces such as plastics, rubbers, wood, leather, metals and glass.

Neil Jarvie, Peratech sales v-p, says that the capability to incorporate pressure sensing that capacitive touch sensing does not provide is important for Tier 1 automotive companies.

The matrix sensors are designed to track multiple touches for position on X and Y axes and independent pressure sensing along the Z-axis.

According to Jarvie, this allows designers to reduce button count in the centre stack, steering wheel and other cockpit surfaces.

“Replace the top surface of buttons with a display, and you have a Human Machine Interface (HMI) that is reconfigurable on the fly,” added Jarvie.

“Because the sensors aren’t affected by the electromagnetic interference of a display, we can make a display panel showing switches, sliders and knobs that actually work.”

The firm’s sensors are tested for operation through cycles of -40 to +100 degrees C, which is the operational temperature range that the automotive industry requires.

“The requirement for a smart force touch display panel, first and foremost, is that is always works,” said Jarvie.

Richard Wilson

Car makers going big on 3D touch control, says UK sensor firm

Car manufacturers are adopting touch control technology in a big way. So much so that UK-based touch sensor firm Peratech has expanded resources in its North Yorkshire-based headquarters.

Car makers going big on 3D touch control, says Peratech

Car makers going big on 3D touch control, says Peratech

The company said it is seeing its QTC force touch sensors being integrated under in-car surfaces such as plastics, rubbers, wood, leather, metals and glass.

Neil Jarvie, Peratech sales v-p, says that the capability to incorporate pressure sensing that capacitive touch sensing does not provide is important for Tier 1 automotive companies.

The matrix sensors are designed to track multiple touches for position on X and Y axes and independent pressure sensing along the Z-axis.

According to Jarvie, this allows designers to reduce button count in the centre stack, steering wheel and other cockpit surfaces.

“Replace the top surface of buttons with a display, and you have a Human Machine Interface (HMI) that is reconfigurable on the fly,” added Jarvie.

“Because the sensors aren’t affected by the electromagnetic interference of a display, we can make a display panel showing switches, sliders and knobs that actually work.”

The firm’s sensors are tested for operation through cycles of -40 to +100 degrees C, which is the operational temperature range that the automotive industry requires.

“The requirement for a smart force touch display panel, first and foremost, is that is always works,” said Jarvie.

Richard Wilson

Synopsys tunes ARC EM processors for low latency apps

Synopsys has added to its processor IP offering with new ARC EM processors with an enhanced instruction set architecture that combines RISC and DSP processing with support for an XY memory system.

Synopsys tunes ARC EM processors for low latency apps

Synopsys tunes ARC EM processors for low latency apps

The EM9D and EM11D processor cores benefit from being able to retrieve instructions and data from memories that are tightly coupled to the processor pipeline. This can reduce the number of accesses to system memory which improves latency.

The ARC MetaWare development tool now offers full C/C++ programming support for the cores’ DSP instructions and XY memory as well as a library of DSP functions.

The toolkit also includes an ITU-T base-ops library for developing voice codecs.

These include FFT and DCT, FIR and IIR filters, as well as vector and matrix math functions.

Likely applications may include speech recognition and audio processing.

EM DSP cores implement a three stage pipeline. These new cores integrate separate X and Y memories with hardware support for address generation and DMA to move data in and out of the memories.

This enables a sustained throughput of one 32×32 MAC operation or two 16×16 MAC operations per clock cycle with minimal energy and area overhead.

These new processors also support full integer, fractional divide and square root operations, unaligned loads/stores and bitstream parsing.

These features enable the EM9D and EM11D to deliver the additional DSP performance required to execute complex sensor algorithms, as well as improve processing efficiency for a range of audio formats including MP3, SBC, OPUS and AAC LC.

 

 

 

Richard Wilson

Synopsys tunes ARC EM processors for low latency apps

Synopsys has added to its processor IP offering with new ARC EM processors with an enhanced instruction set architecture that combines RISC and DSP processing with support for an XY memory system.

imgresThe EM9D and EM11D processor cores benefit from being able to retrieve instructions and data from memories that are tightly coupled to the processor pipeline. This can reduce the number of accesses to system memory which improves latency.

The ARC MetaWare development tool now offers full C/C++ programming support for the cores’ DSP instructions and XY memory as well as a library of DSP functions.

The toolkit also includes an ITU-T base-ops library for developing voice codecs.

These include FFT and DCT, FIR and IIR filters, as well as vector and matrix math functions.

 

Likely applications may include speech recognition and audio processing.

EM DSP cores implement a three stage pipeline. These new cores integrate separate X and Y memories with hardware support for address generation and DMA to move data in and out of the memories.

This enables a sustained throughput of one 32×32 MAC operation or two 16×16 MAC operations per clock cycle with minimal energy and area overhead.

These new processors also support full integer, fractional divide and square root operations, unaligned loads/stores and bitstream parsing.

These features enable the EM9D and EM11D to deliver the additional DSP performance required to execute complex sensor algorithms, as well as improve processing efficiency for a range of audio formats including MP3, SBC, OPUS and AAC LC.

 

 

 

Richard Wilson

Synopsys tunes ARC EM processors for low latency apps

Synopsys has added to its processor IP offering with new ARC EM processors with an enhanced instruction set architecture that combines RISC and DSP processing with support for an XY memory system.

imgresThe EM9D and EM11D processor cores benefit from being able to retrieve instructions and data from memories that are tightly coupled to the processor pipeline. This can reduce the number of accesses to system memory which improves latency.

The ARC MetaWare development tool now offers full C/C++ programming support for the cores’ DSP instructions and XY memory as well as a library of DSP functions.

The toolkit also includes an ITU-T base-ops library for developing voice codecs.

These include FFT and DCT, FIR and IIR filters, as well as vector and matrix math functions.

Likely applications may include speech recognition and audio processing.

EM DSP cores implement a three stage pipeline. These new cores integrate separate X and Y memories with hardware support for address generation and DMA to move data in and out of the memories.

This enables a sustained throughput of one 32×32 MAC operation or two 16×16 MAC operations per clock cycle with minimal energy and area overhead.

These new processors also support full integer, fractional divide and square root operations, unaligned loads/stores and bitstream parsing.

These features enable the EM9D and EM11D to deliver the additional DSP performance required to execute complex sensor algorithms, as well as improve processing efficiency for a range of audio formats including MP3, SBC, OPUS and AAC LC.

 

 

 

Richard Wilson

Synopsys tunes ARC EM processors for low latency apps

Synopsys has added to its processor IP offering with new ARC EM processors with an enhanced instruction set architecture that combines RISC and DSP processing with support for an XY memory system.

Synopsys tunes ARC EM processors for low latency apps

Synopsys tunes ARC EM processors for low latency apps

The EM9D and EM11D processor cores benefit from being able to retrieve instructions and data from memories that are tightly coupled to the processor pipeline. This can reduce the number of accesses to system memory which improves latency.

The ARC MetaWare development tool now offers full C/C++ programming support for the cores’ DSP instructions and XY memory as well as a library of DSP functions.

The toolkit also includes an ITU-T base-ops library for developing voice codecs.

These include FFT and DCT, FIR and IIR filters, as well as vector and matrix math functions.

Likely applications may include speech recognition and audio processing.

EM DSP cores implement a three stage pipeline. These new cores integrate separate X and Y memories with hardware support for address generation and DMA to move data in and out of the memories.

This enables a sustained throughput of one 32×32 MAC operation or two 16×16 MAC operations per clock cycle with minimal energy and area overhead.

These new processors also support full integer, fractional divide and square root operations, unaligned loads/stores and bitstream parsing.

These features enable the EM9D and EM11D to deliver the additional DSP performance required to execute complex sensor algorithms, as well as improve processing efficiency for a range of audio formats including MP3, SBC, OPUS and AAC LC.

 

 

 

Richard Wilson

High speed stacked memory arrives with HBM standard

A stacked memory device which has the potential to achieve memory access speeds 14 times faster than today’s DDR4 has been demonstrated by eSilicon, Northwest Logic and SK Hynix.

proGraphic3The stacked memory device is complaint with the JEDEC 2.5D packaging standard known as high bandwidth memory (HBM).

The chip uses an FPGA-based controller core and PHY for the HBM standard architecture implemented in a Hynix memory array.

eSilicon packaged the FPGA controller designed by Northwest Logic and HBM devices on an organic interposer.

First-generation HBM devices provide eight channels of 128-bit data running at one Gbit/s/pin for a total system throughput of 128Gbyte/s.

According to the companies, they say second-generation HBM devices double the throughput.

They claim this is approximately 14 times the throughput available from a DDR4 DIMM running at 2,600 Mbits/pin. HBM has both power and cost advantages over competing technologies.

Bill Isaacson, senior director, product marketing at eSilicon, writes:

“HBM and system-in-package technology hold great promise to break the power and performance bottlenecks designers are currently facing with regard to memory subsystems.

“This joint effort with Northwest Logic and SK Hynix validates that HBM is ready to enter mainstream use.”

The HBM Controller Core supports both Gen 2 (2 Gbit/s/pin) and Gen 1 (1 Gbit/s/pin).

Brian Daellenbach, president of Northwest Logic, expects to see increasing interest in HBM applications.

 

Richard Wilson

High speed stacked memory arrives with HBM standard

A stacked memory device which has the potential to achieve memory access speeds 14 times faster than today’s DDR4 has been demonstrated by eSilicon, Northwest Logic and SK Hynix.

High speed stacked memory arrives with HBM standard

High speed stacked memory arrives with HBM standard

The stacked memory device is complaint with the JEDEC 2.5D packaging standard known as high bandwidth memory (HBM).

The chip uses an FPGA-based controller core and PHY for the HBM standard architecture implemented in a Hynix memory array.

eSilicon packaged the FPGA controller designed by Northwest Logic and HBM devices on an organic interposer.

First-generation HBM devices provide eight channels of 128-bit data running at one Gbit/s/pin for a total system throughput of 128Gbyte/s.

According to the companies, they say second-generation HBM devices double the throughput.

They claim this is approximately 14 times the throughput available from a DDR4 DIMM running at 2,600 Mbits/pin. HBM has both power and cost advantages over competing technologies.

Bill Isaacson, senior director, product marketing at eSilicon, writes:

“HBM and system-in-package technology hold great promise to break the power and performance bottlenecks designers are currently facing with regard to memory subsystems.

“This joint effort with Northwest Logic and SK Hynix validates that HBM is ready to enter mainstream use.”

The HBM Controller Core supports both Gen 2 (2 Gbit/s/pin) and Gen 1 (1 Gbit/s/pin).

Brian Daellenbach, president of Northwest Logic, expects to see increasing interest in HBM applications.

 

Richard Wilson

High speed stacked memory arrives with HBM standard

A stacked memory device which has the potential to achieve memory access speeds 14 times faster than today’s DDR4 has been demonstrated by eSilicon, Northwest Logic and SK Hynix.

proGraphic3The stacked memory device is complaint with the JEDEC 2.5D packaging standard known as high bandwidth memory (HBM).

The chip uses an FPGA-based controller core and PHY for the HBM standard architecture implemented in a Hynix memory array.

eSilicon packaged the FPGA controller designed by Northwest Logic and HBM devices on an organic interposer.

First-generation HBM devices provide eight channels of 128-bit data running at one Gbit/s/pin for a total system throughput of 128Gbyte/s.

According to the companies, they say second-generation HBM devices double the throughput.

They claim this is approximately 14 times the throughput available from a DDR4 DIMM running at 2,600 Mbits/pin. HBM has both power and cost advantages over competing technologies.

Bill Isaacson, senior director, product marketing at eSilicon, writes:

“HBM and system-in-package technology hold great promise to break the power and performance bottlenecks designers are currently facing with regard to memory subsystems.

“This joint effort with Northwest Logic and SK Hynix validates that HBM is ready to enter mainstream use.”

The HBM Controller Core supports both Gen 2 (2 Gbit/s/pin) and Gen 1 (1 Gbit/s/pin).

Brian Daellenbach, president of Northwest Logic, expects to see increasing interest in HBM applications.

 

Richard Wilson