Dr An Steegen – Imec senior VP process technology

Imec and SPTS Technologies are developing a short cycle-time dry silicon removal and low temperature passivation solution for through-silicon via-middle processing and thinning of the top-wafer in wafer-to-wafer bonding.

Wafer backside processing is critical for 3D-IC wafer stacking. Through-silicon vias (TSV) formed using ‘via-middle’ processing, are typically exposed from the backside of 300mm device wafers by a combination of mechanical grinding and wet or dry etch processes.

Dielectric layers are then deposited by plasma enhanced chemical vapour deposition (PECVD) to passivate and mechanically support the exposed TSVs prior to bump/RDL (redistribution) formation, followed by chip-to-wafer or wafer-to-wafer bonding.

To develop an industrially viable 3D-IC technology, the via reveal process requires a shorter cycle time etching process.

Due to accumulating non-uniformities coming from the TSV frontside etching, bonding and grinding processes, variations of a few microns may occur in residual silicon thickness above the via tips. Therefore, a highly selective process to thin TSV liners and smooth post-etch surfaces is essential to achieve the necessary precision and control within wafer uniformity.

Imec and SPTS are developing a dry etching solution that features in-situ end-point detection. This enables controlled and very precise processing. The process achieves the required TSV height while avoiding lengthy and multiple rework steps thus minimising the overall cost per wafer.

According to Imec, the first results demonstrate that 1,57µm nail height can be controlled within 300nm range.

To follow the via reveal etch step, Imec and SPTS will also work on PECVD dielectric passivation stacks, with SiO and SiN layers deposited at temperatures below 200°C.

Films will be engineered to optimise device electrical performance and stress-managed to minimise warpage of the thin die after debonding.

The collaboration will use SPTS’s Versalis fxP system, a single-wafer cluster platform carrying both etch and dielectric deposition modules to be installed into imec’s 300mm packaging line in Q32015.

Dr An Steegen, senior vice president process technology, Imec writes:

“Equipment suppliers are key in developing an integrated solution for the challenges of scaling technology into advanced nodes, the collaboration with SPTS confirms imec’s direction to accelerate innovation for all our partners by closely interacting with suppliers at an early stage of development.”

Imec’s research into 3D-IC includes partners such as Globalfoundries, Intel, Micron, Panasonic, Samsung, SK Hynix, Sony, and TSMC.

david manners

Dr An Steegen – Imec senior VP process technology

Imec and SPTS Technologies are developing a short cycle-time dry silicon removal and low temperature passivation solution for through-silicon via-middle processing and thinning of the top-wafer in wafer-to-wafer bonding.

Wafer backside processing is critical for 3D-IC wafer stacking. Through-silicon vias (TSV) formed using ‘via-middle’ processing, are typically exposed from the backside of 300mm device wafers by a combination of mechanical grinding and wet or dry etch processes.

Dielectric layers are then deposited by plasma enhanced chemical vapour deposition (PECVD) to passivate and mechanically support the exposed TSVs prior to bump/RDL (redistribution) formation, followed by chip-to-wafer or wafer-to-wafer bonding.

To develop an industrially viable 3D-IC technology, the via reveal process requires a shorter cycle time etching process.

Due to accumulating non-uniformities coming from the TSV frontside etching, bonding and grinding processes, variations of a few microns may occur in residual silicon thickness above the via tips. Therefore, a highly selective process to thin TSV liners and smooth post-etch surfaces is essential to achieve the necessary precision and control within wafer uniformity.

Imec and SPTS are developing a dry etching solution that features in-situ end-point detection. This enables controlled and very precise processing. The process achieves the required TSV height while avoiding lengthy and multiple rework steps thus minimising the overall cost per wafer.

According to Imec, the first results demonstrate that 1,57µm nail height can be controlled within 300nm range.

To follow the via reveal etch step, Imec and SPTS will also work on PECVD dielectric passivation stacks, with SiO and SiN layers deposited at temperatures below 200°C.

Films will be engineered to optimise device electrical performance and stress-managed to minimise warpage of the thin die after debonding.

The collaboration will use SPTS’s Versalis fxP system, a single-wafer cluster platform carrying both etch and dielectric deposition modules to be installed into imec’s 300mm packaging line in Q32015.

Dr An Steegen, senior vice president process technology, Imec writes:

“Equipment suppliers are key in developing an integrated solution for the challenges of scaling technology into advanced nodes, the collaboration with SPTS confirms imec’s direction to accelerate innovation for all our partners by closely interacting with suppliers at an early stage of development.”

Imec’s research into 3D-IC includes partners such as Globalfoundries, Intel, Micron, Panasonic, Samsung, SK Hynix, Sony, and TSMC.

david manners