Flex Logix is offering evaluation licences to SoC designers for block RAM and DSP cores which can be added to its embedded FPGA fabric.
Flex Logix’ technology allows system-on-chip SoC designers to embed field FPGA blocks, so allowing SoCs to be optimized or customized after the device is fabbed.
By adding block RAM and DSP, Flex Logix expands the tool kit available to designers for this post-production flexibility.
Applications such as encryption, networking and signal processing require blocks of RAM to be integrated into the FPGA to provide fast local memory to implement buffers, scratchpads, FIFOs, and other low-latency memory that improves performance.
While traditional FPGAs typically offer one type and size of RAM that can “emulate” different widths, Flex Logix’ Block RAM architecture can provide exactly the type and amount of memory an application requires.
This flexibility is accomplished by inserting block RAM between the logic cores—which “tile” together to make an array—controlling them with otherwise unused inward-facing inter-tile I/Os.
Flex Logix can support single-port RAM or dual-port RAM, any width, any amount; ECC, parity or no error checking; even MBIST—offering more flexibility than available in discrete FPGA chips.
In addition to local memory, many applications also require digital signal processing DSP capability. Wireless base station digital front ends, image and audio processing, and other applications require high-performance DSP functions such as Finite Impulse Response (FIR) filters, Infinite Impulse Response (IIR) filters, and Fast Fourier Transforms (FFT).
The basic building block for implementing these DSP functions is a pre-adder/multiplier/accumulator (MAC).
Flex Logix now offers an EFLX Logic core that incorporates 40 MACs with 22-bit inputs and 48-bit accumulation. The MACs can be combined for 2x precision and pipelined for high throughput. They can also be used as complex-number MACs for certain DSP algorithms.
Performance specs for a single Flex Logix’ DSP core are similar to that of existing stand-alone 28nm FPGA chips, achieving 500 Msamples/second for a 22-bit 5-tap FIR and 300 Msamples/second for a 22-bit 40-tap FIR. Multiple EFLX DSP cores can be combined to implement more complex DSP functions.
The EFLX Compiler maps standard Verilog/RTL into the EFLX array, including DSP and Block RAM (and even including external Block RAM if desired).
Customers do not require any FPGA expertise to use Flex Logix technology, says Flex Logix.
david manners
