Author Archives: david manners

Sondrel joins Imec IC-link

Sondrel joins Imec IC-link

Sondrel, the Reading SoC design specialist, has joined Imec’s IC-link partnership programme in which a number of companies make their particular skill-sets available to realise an IC design project. “Building and creating relationships within the industry is more critical than ever,” says Sondrel CEO Graham Curren, “as we seek to provide the best solutions for ...

David Manners

ARM takes 64-bit to power-constrained embedded applications

ARM takes 64-bit to power-constrained embedded applications

ARM has extended its 64-bit architecture into power-constrained embedded applications such as single-board computers and automotive with the Cortex-A35. ARM says thst the A35 is “the most efficient Cortex-A class CPU ever designed by ARM.” It delivers an average of 20% greater performance and efficiency across a range of 32-bit mobile workloads relative to Cortex-A7 ...

David Manners

Plessey and 8point3 design lighting range

Plessey and 8point3 design lighting range

Plessey  is collaborating with solid-state lighting specialist 8Point3 to develop and produce an architectural lighting product range using Plessey’s MaGIC GaN-on-Silicon LEDs. The Sabre linear lighting products combine the benefits of remote phosphor with an LED light engine to provide a uniform and diffuse luminance and appearance, ensuring no reflections or pixilation, even when dimming the ...

David Manners

CEVA adopts UltraSoc debugger

CEVA adopts UltraSoc debugger

CEVA is to make the UltraSoc debugger available for its DSP cores. UltraSoC’s  debugger solution enables SoC developers to build an on-chip monitoring, control and communications architecture that ‘looks inside’ the chip while the device is operating. This helps identify and eliminate bugs, speeding up time to market. It can also be used after deployment for in-field performance monitoring ...

David Manners

GloFo adopts ATopTech FD-SOI physical design tools

GloFo adopts ATopTech FD-SOI physical design tools

ATopTech, the physical design specialist, have had their Aprisa and Apogee Place & Route tools now enabled for the current version of the GLoFo’s 22FDX FD-SOI platform reference flow. GloFo has qualified these tools for the 22FDX reference flow to provide customers with the design flexibility of using body bias to manage power, performance and leakage. ...

David Manners

GloFo achieves first pass 14nm silicon

GloFo achieves first pass 14nm silicon

Globalfoundries says it has achieved first-pass silicon on its 14nm finfet process. AMD has taped out multiple products using GloFo’s 14nm Low Power Plus (14LPP) process technology and is currently conducting validation work on 14LPP production samples. GloFo reckons high-volume production on 14nm LPP will start in 2016. “We expect to leverage the advanced 14LPP process ...

David Manners

21st Century UltraSoC

21st Century UltraSoC

UltraSoC , the SoC on-chip monitoring and analytics specialist, has enhanced its product to allow users to integrate legacy signal-based systems with the company’s message-based architecture. This is particularly useful for designers working with ARM cores and its associated debug system, CoreSight. “UltraSoC is a 21st-century solution to the growing crisis in chip design,” says ...

David Manners